From 17c5f70598a96422f9d98eab4316bfe48d4bb2ba Mon Sep 17 00:00:00 2001 From: Nick Gasson Date: Mon, 5 Feb 2018 19:50:23 +0000 Subject: [PATCH] Fix error passing signal alias to procedure. Fixes #340 --- src/sem.c | 16 +++++----- test/regress/issue340.vhd | 61 +++++++++++++++++++++++++++++++++++++++ test/regress/testlist.txt | 1 + test/sem/issue340.vhd | 61 +++++++++++++++++++++++++++++++++++++++ test/test_sem.c | 11 +++++++ 5 files changed, 142 insertions(+), 8 deletions(-) create mode 100644 test/regress/issue340.vhd create mode 100644 test/sem/issue340.vhd diff --git a/src/sem.c b/src/sem.c index d4c3a9cc..745cc90b 100644 --- a/src/sem.c +++ b/src/sem.c @@ -3917,15 +3917,15 @@ static bool sem_check_call_args(tree_t t, tree_t decl) tree_t value = tree_value(param); tree_kind_t kind = tree_kind(value); - while ((kind == T_ARRAY_REF) || (kind == T_ARRAY_SLICE) - || (kind == T_ALL) || (kind == T_RECORD_REF)) { - value = tree_value(value); - kind = tree_kind(value); - } - if (kind == T_REF && tree_kind(tree_ref(value)) == T_ALIAS) { - value = tree_value(tree_ref(value)); - kind = tree_kind(value); + while (kind == T_ARRAY_REF || kind == T_ARRAY_SLICE + || kind == T_ALL || kind == T_RECORD_REF + || (kind == T_REF && tree_kind(tree_ref(value)) == T_ALIAS)) { + if (kind == T_REF) + value = tree_value(tree_ref(value)); + else + value = tree_value(value); + kind = tree_kind(value); } if (class == C_SIGNAL) { diff --git a/test/regress/issue340.vhd b/test/regress/issue340.vhd new file mode 100644 index 00000000..a63b39a3 --- /dev/null +++ b/test/regress/issue340.vhd @@ -0,0 +1,61 @@ +entity submodule is + port ( + sig : in bit); +end entity; + +architecture a of submodule is +begin + main : process + begin + wait for 1 ns; + assert sig = '1'; + report "Success"; + wait; + end process; +end; + +entity issue340 is +end entity; + +architecture a of issue340 is + signal sig_vector : bit_vector(0 to 1) := "00"; + alias sig_bit_alias : bit is sig_vector(0); + + signal sig : bit := '0'; + alias sig_alias : bit is sig; + + procedure drive(signal value : out bit) is + begin + value <= '1'; + end; +begin + + main : process + begin + drive(sig_alias); + drive(sig_bit_alias); + wait for 1 ns; + assert sig_vector(0) = '1'; + assert sig = '1'; + assert sig_alias = '1'; + assert sig_bit_alias = '1'; + report "Success"; + wait; + end process; + + submodule0_inst : entity work.submodule + port map ( + sig => sig_alias); + + submodule1_inst : entity work.submodule + port map ( + sig => sig_bit_alias); + + submodule2_inst : entity work.submodule + port map ( + sig => sig); + + submodule3_inst : entity work.submodule + port map ( + sig => sig_vector(0)); +end; diff --git a/test/regress/testlist.txt b/test/regress/testlist.txt index 4c8f6c38..e1bebda4 100644 --- a/test/regress/testlist.txt +++ b/test/regress/testlist.txt @@ -341,3 +341,4 @@ issue351 normal,gold issue367 normal issue369 normal issue293 normal +issue340 normal diff --git a/test/sem/issue340.vhd b/test/sem/issue340.vhd new file mode 100644 index 00000000..edfc4c40 --- /dev/null +++ b/test/sem/issue340.vhd @@ -0,0 +1,61 @@ +entity submodule is + port ( + sig : in bit); +end entity; + +architecture a of submodule is +begin + main : process + begin + wait for 1 ns; + assert sig = '1'; + report "Success"; + wait; + end process; +end; + +entity bug is +end entity; + +architecture a of bug is + signal sig_vector : bit_vector(0 to 1) := "00"; + alias sig_bit_alias : bit is sig_vector(0); + + signal sig : bit := '0'; + alias sig_alias : bit is sig; + + procedure drive(signal value : out bit) is + begin + value <= '1'; + end; +begin + + main : process + begin + drive(sig_alias); + drive(sig_bit_alias); + wait for 1 ns; + assert sig_vector(0) = '1'; + assert sig = '1'; + assert sig_alias = '1'; + assert sig_bit_alias = '1'; + report "Success"; + wait; + end process; + + submodule0_inst : entity work.submodule + port map ( + sig => sig_alias); + + submodule1_inst : entity work.submodule + port map ( + sig => sig_bit_alias); + + submodule2_inst : entity work.submodule + port map ( + sig => sig); + + submodule3_inst : entity work.submodule + port map ( + sig => sig_vector(0)); +end; diff --git a/test/test_sem.c b/test/test_sem.c index 90395710..168fb52e 100644 --- a/test/test_sem.c +++ b/test/test_sem.c @@ -1916,6 +1916,16 @@ START_TEST(test_issue341) } END_TEST +START_TEST(test_issue340) +{ + input_from_file(TESTDIR "/sem/issue340.vhd"); + + parse_and_check(T_ENTITY, T_ARCH, T_ENTITY, T_ARCH); + + fail_unless(sem_errors() == 0); +} +END_TEST + Suite *get_sem_tests(void) { Suite *s = suite_create("sem"); @@ -2015,6 +2025,7 @@ Suite *get_sem_tests(void) tcase_add_test(tc_core, test_issue326); tcase_add_test(tc_core, test_issue232); tcase_add_test(tc_core, test_issue341); + tcase_add_test(tc_core, test_issue340); suite_add_tcase(s, tc_core); return s; -- 2.39.2