From 3d08d6954b53942ad2d05099eb42bddec6e04466 Mon Sep 17 00:00:00 2001 From: Nick Gasson Date: Fri, 12 Jan 2024 19:32:33 +0000 Subject: [PATCH] Fix incorrect aggregate direction with range association. Fixes #826 --- src/lower.c | 18 +++++--- test/regress/issue826.vhd | 88 +++++++++++++++++++++++++++++++++++++++ test/regress/testlist.txt | 1 + 3 files changed, 101 insertions(+), 6 deletions(-) create mode 100644 test/regress/issue826.vhd diff --git a/src/lower.c b/src/lower.c index 9ef03ac5..cd51a3c5 100644 --- a/src/lower.c +++ b/src/lower.c @@ -3810,7 +3810,9 @@ static vcode_reg_t lower_aggregate_bounds(lower_unit_t *lu, tree_t expr, const int nassocs = tree_assocs(expr); - const bool pos_concat = (standard() >= STD_08 && dimension_of(type) == 1); + const bool vhdl2008_slice = + standard() >= STD_08 && dimension_of(type) == 1; + int64_t pos = 0; bool known_elem_count = true; for (int i = 0; i < nassocs; i++) { @@ -3843,10 +3845,14 @@ static vcode_reg_t lower_aggregate_bounds(lower_unit_t *lu, tree_t expr, else known_elem_count = false; - // VHDL-2008 range association determines index direction - // for unconstrained aggregate - if (standard() >= STD_08) - dir = rkind; + if (vhdl2008_slice) { + // VHDL-2008 range association determines index + // direction for unconstrained aggregate when the + // expression type matches the array type + type_t value_type = tree_type(tree_value(a)); + if (type_eq(type, value_type)) + dir = rkind; + } } else known_elem_count = false; @@ -3860,7 +3866,7 @@ static vcode_reg_t lower_aggregate_bounds(lower_unit_t *lu, tree_t expr, case A_POS: { int64_t length = 1; - if (pos_concat) { + if (vhdl2008_slice) { type_t value_type = tree_type(tree_value(a)); if (type_eq(type, value_type)) length = lower_array_const_size(value_type); diff --git a/test/regress/issue826.vhd b/test/regress/issue826.vhd new file mode 100644 index 00000000..447e9aa5 --- /dev/null +++ b/test/regress/issue826.vhd @@ -0,0 +1,88 @@ +library IEEE ; +use ieee.std_logic_1164.all ; +use ieee.numeric_std.all ; + +entity issue826 is +end entity ; +architecture test of issue826 is + constant ZERO : std_logic_vector(7 downto 0) := X"00" ; + constant ZERO_UV : unsigned(0 to 7) := X"00" ; +begin + TestProc : process + variable SLV : std_logic_vector(7 downto 0) ; + variable SLVR : std_logic_vector(0 to 7) ; + variable UV : unsigned(0 to 7) ; + variable SL : std_logic ; + begin + SLV := (others => '0') ; + assert SLV = X"00" report to_hstring(SLV); + + SLV := (7 downto 0 => '0') ; + assert SLV = X"00" report to_hstring(SLV); + + SLV := ('0','0','0','0','0','0','0','0') ; + assert SLV = X"00" report to_hstring(SLV); + + SLV := ((7|6 =>'0', 5 downto 0 =>'0')) ; + assert SLV = X"00" report to_hstring(SLV); + + SLV := (7|6 =>'1', 5 downto 0 =>'0') ; + assert SLV = X"C0" report to_hstring(SLV); + + SLV := (0 to 5 =>'0', 6 =>'1', 7 =>'1') ; + assert SLV = X"C0" report to_hstring(SLV); + + SLVR := (7|6 =>'1', 5 downto 0 =>'0') ; + assert SLVR = X"03" report to_hstring(SLV); + + SLVR := (0 to 5 =>'0', 6 =>'1', 7 =>'1') ; + assert SLVR = X"03" report to_hstring(SLV); + + SLV := not((0 to 5 =>'0', 6 =>'1', 7 =>'1')) ; + assert SLV = X"FC" report to_hstring(SLV); + + UV := not((0 to 5 =>'0', 6 =>'1', 7 =>'1')) ; + assert SLV = X"FC" report to_hstring(SLV); + + SLV := not((7 =>'1', 6 =>'1', 5 downto 0 =>'0')) ; + assert SLV = X"FC" report to_hstring(SLV); + + UV := not((7 =>'1', 6 =>'1', 5 downto 0 =>'0')) ; + assert SLV = X"FC" report to_hstring(SLV); + + SLV := ZERO or (7|6 =>'1', 5 downto 0 =>'0') ; + assert SLV = X"03" report to_hstring(SLV); + + SLV := ZERO or (0 to 5 =>'0', 6 =>'1', 7 =>'1') ; + assert SLV = X"03" report to_hstring(SLV); + + SLV := (0 to 5 =>'0', 6 =>'1', 7 =>'1') or ZERO ; + assert SLV = X"03" report to_hstring(SLV); + + UV := ZERO_UV or (7|6 =>'1', 5 downto 0 =>'0') ; + assert UV = X"03" report to_hstring(SLV); + + UV := ZERO_UV or (0 to 5 =>'0', 6 =>'1', 7 =>'1') ; + assert UV = X"03" report to_hstring(SLV); + + UV := (0 to 5 =>'0', 6 =>'1', 7 =>'1') or ZERO_UV ; + assert UV = X"03" report to_hstring(SLV); + + UV := ZERO_UV + (7|6 =>'1', 5 downto 0 =>'0') ; + assert UV = X"03" report to_hstring(SLV); + + UV := ZERO_UV + (0 to 5 =>'0', 6 =>'1', 7 =>'1') ; + assert UV = X"03" report to_hstring(SLV); + + UV := (0 to 5 =>'0', 6 =>'1', 7 =>'1') + ZERO_UV ; + assert UV = X"03" report to_hstring(SLV); + + SL := "not"(not(std_logic_vector'(0 to 5 =>'0', 6 =>'1', 7 =>'1')))(7) ; + assert SL = '1'; + + SL := "not"(not(unsigned'(0 to 5 =>'0', 6 =>'1', 7 =>'1')))(7) ; + assert SL = '0'; + + wait ; + end process TestProc ; +end architecture test ; diff --git a/test/regress/testlist.txt b/test/regress/testlist.txt index f7326e3a..e7a794fd 100644 --- a/test/regress/testlist.txt +++ b/test/regress/testlist.txt @@ -919,3 +919,4 @@ issue819 normal,2008 issue820 normal issue824 normal issue825 normal +issue826 normal,2008 -- 2.39.2