From 7355fb45edba14fdd94525ee1afe246821785479 Mon Sep 17 00:00:00 2001
From: Nick Gasson <nick@nickg.me.uk>
Date: Sat, 19 Nov 2022 21:34:52 +0000
Subject: [PATCH] Fix bug with VHDL-2008 aggregate index direction

---
 src/bounds.c                                 |  6 +++
 test/regress/testlist.txt                    |  3 +-
 test/regress/{vecorder.vhd => vecorder1.vhd} | 10 ++--
 test/regress/vecorder2.vhd                   | 54 ++++++++++++++++++++
 4 files changed, 67 insertions(+), 6 deletions(-)
 rename test/regress/{vecorder.vhd => vecorder1.vhd} (94%)
 create mode 100644 test/regress/vecorder2.vhd

diff --git a/src/bounds.c b/src/bounds.c
index 7617af7e..1925a8ca 100644
--- a/src/bounds.c
+++ b/src/bounds.c
@@ -572,6 +572,12 @@ static void bounds_check_aggregate(tree_t t)
                   bounds_error(a, "discrete range has %"PRIi64" elements but "
                                "length of expression is %"PRIi64,
                                ihigh - ilow + 1, count);
+               else if (unconstrained && count > 1) {
+                  // VHDL-2008 range association determines index
+                  // direction for unconstrained aggregate
+                  assert(standard() >= STD_08);
+                  dir = rkind;
+               }
             }
             else
                known_elem_count = false;
diff --git a/test/regress/testlist.txt b/test/regress/testlist.txt
index f22c3aaa..84b5031c 100644
--- a/test/regress/testlist.txt
+++ b/test/regress/testlist.txt
@@ -18,7 +18,7 @@ image           gold,normal
 cond1           gold,normal
 counter         normal,stop=50ns,gold
 cond2           gold,normal
-vecorder        normal
+vecorder1       normal
 elab2           normal
 func1           normal
 signal5         normal
@@ -691,3 +691,4 @@ issue560        normal,2008
 issue570        normal,2008
 issue571        normal,2008,relaxed
 operator6       normal,2008
+vecorder2       normal,2008
diff --git a/test/regress/vecorder.vhd b/test/regress/vecorder1.vhd
similarity index 94%
rename from test/regress/vecorder.vhd
rename to test/regress/vecorder1.vhd
index badbef88..12d66d56 100644
--- a/test/regress/vecorder.vhd
+++ b/test/regress/vecorder1.vhd
@@ -1,7 +1,7 @@
-entity vecorder is
+entity vecorder1 is
 end entity;
 
-architecture test of vecorder is
+architecture test of vecorder1 is
     type int_array is array (integer range <>) of integer;
 
     signal s : int_array(0 to 1) := ( 0 => 0, 1 => 1 );
@@ -21,7 +21,7 @@ begin
         assert x(1) = 3 report "four";
         assert x = ( 2, 3 ) report "five";
         assert ( 2, 3 ) = x report "six";
-        
+
         assert s(0) = 0 report "s one";
         assert s(1) = 1 report "s two";
         s <= ( 2, 3 );
@@ -40,8 +40,8 @@ begin
         assert y(0) = 3 report "y three";
         assert y(1) = 2 report "y four";
         assert y = ( 2, 3 ) report "y five";
-        
+
         wait;
     end process;
-    
+
 end architecture;
diff --git a/test/regress/vecorder2.vhd b/test/regress/vecorder2.vhd
new file mode 100644
index 00000000..ba30384f
--- /dev/null
+++ b/test/regress/vecorder2.vhd
@@ -0,0 +1,54 @@
+library ieee;
+use ieee.numeric_std.all;
+use ieee.std_logic_1164.all;
+
+
+entity vecorder2 is
+
+end vecorder2;
+
+architecture rtl of vecorder2 is
+    signal c_a : std_logic_vector(11 downto 0) := x"FAE";
+    signal c_b : std_logic_vector(11 downto 0) := x"182";
+
+    signal s_expected_vector : std_logic_vector(31 downto 0);
+    signal s_resulting_vector : std_logic_vector(31 downto 0);
+begin
+    -- Compute expected value using intermediate variables for padding
+    expected_value : process
+        variable v_a_padded : std_logic_vector(15 downto 0);
+        variable v_b_padded : std_logic_vector(15 downto 0);
+    begin
+        v_a_padded := (15 downto 12 => c_a(11), 11 downto 0 => c_a);
+        v_b_padded := (15 downto 12 => c_b(11), 11 downto 0 => c_b);
+
+        s_expected_vector <= v_a_padded & v_b_padded;
+
+        wait for 1 ns;
+
+        report "Expected result " & to_hstring(s_expected_vector) severity note;
+
+        wait;
+    end process;
+
+    -- Perform the concatenation and the padding in 1 line
+    resulting_value : process
+    begin
+        s_resulting_vector <=
+            (15 downto 12 => c_a(11), 11 downto 0 => c_a) &
+            (15 downto 12 => c_b(11), 11 downto 0 => c_b);
+
+        wait for 2 ns;
+
+        report "Actual result " & to_hstring(s_resulting_vector) severity note;
+
+        wait;
+    end process;
+
+    checker : process
+    begin
+        wait for 3 ns;
+        assert s_resulting_vector = s_expected_vector severity failure;
+        wait;
+    end process;
+end rtl;
-- 
2.39.2