From f1c44eb4a28e6ae957239af56ca84064963492b9 Mon Sep 17 00:00:00 2001 From: Nick Gasson Date: Thu, 17 Nov 2022 21:04:27 +0000 Subject: [PATCH] Add peephole optimisations for SUB opcode --- src/jit/jit-core.c | 2 ++ src/jit/jit-optim.c | 20 ++++++++++++++++++++ test/test_jit.c | 11 +++++++++++ 3 files changed, 33 insertions(+) diff --git a/src/jit/jit-core.c b/src/jit/jit-core.c index bc0435f0..d38668b3 100644 --- a/src/jit/jit-core.c +++ b/src/jit/jit-core.c @@ -1062,6 +1062,8 @@ jit_handle_t jit_assemble(jit_t *j, ident_t name, const char *text) { "T", JIT_CC_T }, { "F", JIT_CC_F }, { "EQ", JIT_CC_EQ }, + { "O", JIT_CC_O }, + { "C", JIT_CC_C }, }; f->bufsz = 128; diff --git a/src/jit/jit-optim.c b/src/jit/jit-optim.c index 00d9a80b..a1ca2936 100644 --- a/src/jit/jit-optim.c +++ b/src/jit/jit-optim.c @@ -497,6 +497,19 @@ static void jit_lvn_sub(jit_ir_t *ir, lvn_state_t *state) #undef FOLD_SUB } + if (ir->arg2.kind == JIT_VALUE_INT64 && ir->arg2.int64 == 0) { + lvn_mov_reg(ir, state, ir->arg1.reg); + return; + } + else if (ir->arg1.kind == JIT_VALUE_INT64 && ir->arg1.int64 == 0 + && ir->cc == JIT_CC_NONE && ir->size == JIT_SZ_UNSPEC) { + ir->op = J_NEG; + ir->arg1 = ir->arg2; + ir->arg2.kind = JIT_VALUE_INVALID; + jit_lvn_generic(ir, state); + return; + } + jit_lvn_generic(ir, state); } @@ -519,6 +532,12 @@ static void jit_lvn_copy(jit_ir_t *ir, lvn_state_t *state) state->regvn[ir->result] = state->nextvn++; } +static void jit_lvn_bzero(jit_ir_t *ir, lvn_state_t *state) +{ + // Clobbers the count register + state->regvn[ir->result] = state->nextvn++; +} + void jit_do_lvn(jit_func_t *f) { lvn_state_t state = { @@ -546,6 +565,7 @@ void jit_do_lvn(jit_func_t *f) case J_SUB: jit_lvn_sub(ir, &state); break; case J_MOV: jit_lvn_mov(ir, &state); break; case MACRO_COPY: jit_lvn_copy(ir, &state); break; + case MACRO_BZERO: jit_lvn_bzero(ir, &state); break; default: break; } } diff --git a/test/test_jit.c b/test/test_jit.c index 132a549a..672927fd 100644 --- a/test/test_jit.c +++ b/test/test_jit.c @@ -1298,6 +1298,9 @@ START_TEST(test_lvn1) " MUL R1, #1, R2 \n" " MUL R1, #0, R2 \n" " ADD R1, R1, #0 \n" + " SUB R1, R1, #0 \n" + " SUB R1, #0, R1 \n" + " SUB.O R1, #0, R1 \n" " RET \n"; jit_handle_t h1 = jit_assemble(j, ident_new("myfunc"), text1); @@ -1335,6 +1338,14 @@ START_TEST(test_lvn1) ck_assert_int_eq(f->irbuf[12].op, J_NOP); + ck_assert_int_eq(f->irbuf[13].op, J_NOP); + + ck_assert_int_eq(f->irbuf[14].op, J_NEG); + ck_assert_int_eq(f->irbuf[14].arg1.kind, JIT_VALUE_REG); + ck_assert_int_eq(f->irbuf[14].arg1.reg, 1); + + ck_assert_int_eq(f->irbuf[15].op, J_SUB); + jit_free(j); } END_TEST -- 2.39.2