]> Nick Gasson's Git Repositories - nvc.git/commit
Add conversion functions for Verilog/VHDL interface boundary
authorNick Gasson <nick@nickg.me.uk>
Wed, 25 Oct 2023 20:02:13 +0000 (21:02 +0100)
committerNick Gasson <nick@nickg.me.uk>
Wed, 25 Oct 2023 20:25:26 +0000 (21:25 +0100)
commit12b95498d124ea6cfdf49d516d7dca8d3cacc6a5
treecbf81bd175b3900143ec8f4a06dd2901a7de0a7b
parent9c08398dceae1d8985ce752d6576ef66d5a0bb1a
Add conversion functions for Verilog/VHDL interface boundary
lib/nvc.08/deps.mk
lib/nvc.19/deps.mk
lib/nvc/deps.mk
lib/nvc/verilog-body.vhd
lib/nvc/verilog.vhd
src/vcode.c
src/vlog/vlog-lower.c
test/regress/mixed1.v [new file with mode: 0644]
test/regress/mixed1.vhd [new file with mode: 0644]
test/regress/testlist.txt