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(parent: 9c08398) | patch

author	Nick Gasson <nick@nickg.me.uk>
	Wed, 25 Oct 2023 20:02:13 +0000 (21:02 +0100)
committer	Nick Gasson <nick@nickg.me.uk>
	Wed, 25 Oct 2023 20:25:26 +0000 (21:25 +0100)
commit	12b95498d124ea6cfdf49d516d7dca8d3cacc6a5
tree	cbf81bd175b3900143ec8f4a06dd2901a7de0a7b	tree \| snapshot
parent	9c08398dceae1d8985ce752d6576ef66d5a0bb1a	commit \| diff

Add conversion functions for Verilog/VHDL interface boundary

lib/nvc.08/deps.mk		diff \| blob \| history
lib/nvc.19/deps.mk		diff \| blob \| history
lib/nvc/deps.mk		diff \| blob \| history
lib/nvc/verilog-body.vhd		diff \| blob \| history
lib/nvc/verilog.vhd		diff \| blob \| history
src/vcode.c		diff \| blob \| history
src/vlog/vlog-lower.c		diff \| blob \| history
test/regress/mixed1.v	[new file with mode: 0644]	blob
test/regress/mixed1.vhd	[new file with mode: 0644]	blob
test/regress/testlist.txt		diff \| blob \| history

VHDL compiler and simulator