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description	VHDL compiler and simulator
owner	Nick Gasson
last change	Thu, 25 Apr 2024 20:52:48 +0000 (21:52 +0100)

4 hours ago	Nick Gasson	Improve duplicate check when generating sensitivity... master github/master sr.ht/master	commit \| commitdiff \| tree \| snapshot
4 hours ago	Nick Gasson	Fix assertion failure with procedure declared inside...	commit \| commitdiff \| tree \| snapshot
29 hours ago	Nick Gasson	Fix spurious error with generic package types in port...	commit \| commitdiff \| tree \| snapshot
2 days ago	Nick Gasson	Verilog "forever" loops	commit \| commitdiff \| tree \| snapshot
2 days ago	Nick Gasson	Verilog unary negation	commit \| commitdiff \| tree \| snapshot
4 days ago	Nick Gasson	Use saturating addition for coverage counters. Issue...	commit \| commitdiff \| tree \| snapshot
5 days ago	Nick Gasson	Lowering for delays in Verilog procedural assignments	commit \| commitdiff \| tree \| snapshot
7 days ago	Nick Gasson	Use deposits for Verilog blocking assignments	commit \| commitdiff \| tree \| snapshot
7 days ago	Nick Gasson	Parsing for delay in Verilog procedural assignments	commit \| commitdiff \| tree \| snapshot
7 days ago	Nick Gasson	Plug several memory leaks	commit \| commitdiff \| tree \| snapshot
7 days ago	Nick Gasson	Revert "If/case statements do not count for statement...	commit \| commitdiff \| tree \| snapshot
8 days ago	Nick Gasson	Speed up lock acquisition in uncontended case	commit \| commitdiff \| tree \| snapshot
11 days ago	Nick Gasson	Refactor statement coverage emission	commit \| commitdiff \| tree \| snapshot
11 days ago	Nick Gasson	If/case statements do not count for statement coverage	commit \| commitdiff \| tree \| snapshot
11 days ago	Nick Gasson	Add some labels to blocks in cover9 test	commit \| commitdiff \| tree \| snapshot
12 days ago	Nick Gasson	Merge duplicated irgen_op_cover_stmt and irgen_op_cover...	commit \| commitdiff \| tree \| snapshot
...

2 weeks ago	r1.12.0	Release 1.12.0	tag	\| commit \| shortlog \| log
2 months ago	r1.11.3	Release 1.11.3	tag	\| commit \| shortlog \| log
3 months ago	r1.11.2	Release 1.11.2	tag	\| commit \| shortlog \| log
4 months ago	r1.11.1	Release 1.11.1	tag	\| commit \| shortlog \| log
4 months ago	r1.11.0	Release 1.11.0	tag	\| commit \| shortlog \| log
6 months ago	r1.10.4	Release 1.10.4	tag	\| commit \| shortlog \| log
7 months ago	r1.10.3	Release 1.10.3	tag	\| commit \| shortlog \| log
8 months ago	r1.10.2	Release 1.10.2	tag	\| commit \| shortlog \| log
8 months ago	r1.10.1	Release 1.10.1	tag	\| commit \| shortlog \| log
9 months ago	r1.10.0	Release 1.10.0	tag	\| commit \| shortlog \| log
11 months ago	r1.9.2	Release 1.9.2	tag	\| commit \| shortlog \| log
12 months ago	r1.9.1	Release 1.9.1	tag	\| commit \| shortlog \| log
12 months ago	r1.9.0	Release 1.9.0	tag	\| commit \| shortlog \| log
14 months ago	r1.8.2	Release 1.8.2	tag	\| commit \| shortlog \| log
15 months ago	r1.8.1	Release 1.8.1	tag	\| commit \| shortlog \| log
15 months ago	r1.8.0	Release 1.8.0	tag	\| commit \| shortlog \| log
...

3 hours ago	v1.12-branch	shortlog \| log \| tree
4 hours ago	master	shortlog \| log \| tree
11 days ago	ucis	shortlog \| log \| tree
2 months ago	v1.11-branch	shortlog \| log \| tree
5 months ago	gui	shortlog \| log \| tree
6 months ago	v1.10-branch	shortlog \| log \| tree
8 months ago	lazy-predefs	shortlog \| log \| tree
9 months ago	lazy-lower	shortlog \| log \| tree
10 months ago	issue709	shortlog \| log \| tree
11 months ago	v1.9-branch	shortlog \| log \| tree
12 months ago	jit-compile-all	shortlog \| log \| tree
12 months ago	flatten-array-access	shortlog \| log \| tree
14 months ago	v1.8-branch	shortlog \| log \| tree
15 months ago	aotgen	shortlog \| log \| tree
16 months ago	libdwarf	shortlog \| log \| tree
18 months ago	v1.7-branch	shortlog \| log \| tree
...

VHDL compiler and simulator