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(parent: 5a13bbb) | patch

author	Nick Gasson <nick@nickg.me.uk>
	Tue, 18 Jun 2024 18:51:27 +0000 (19:51 +0100)
committer	Nick Gasson <nick@nickg.me.uk>
	Tue, 18 Jun 2024 18:53:03 +0000 (19:53 +0100)
commit	143bbf5965a7cfff3ee30ec4d9f197ea2cce3393
tree	6981edebaa1314d29060e1e543160dc2c366e266	tree
parent	5a13bbbd581df29dd6d730ad99fb273ddb6b7f35	commit \| diff

Fix parsing of non-ANSI Verilog port declarations. Issue 811

src/vlog/vlog-parse.y		diff \| blob \| history
test/test_vlog.c		diff \| blob \| history
test/vlog/ports.v		diff \| blob \| history

VHDL compiler and simulator