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(parent: a56ea54) | patch

author	Nick Gasson <nick@nickg.me.uk>
	Sat, 17 Jun 2023 16:45:47 +0000 (17:45 +0100)
committer	Nick Gasson <nick@nickg.me.uk>
	Sat, 17 Jun 2023 16:45:47 +0000 (17:45 +0100)
commit	1622149c83f4f2fa46a541bd2fc5ab547d8b30db
tree	7d6adde0e4fc9251007fe25756324fe15c9a32c4	tree \| snapshot
parent	a56ea54999f6df1f5b325395b2bb3cd38da1987f	commit \| diff

Merge analyse_vhdl/analyse_verilog into analyse_file

src/common.c		diff \| blob \| history
src/common.h		diff \| blob \| history
src/lib.c		diff \| blob \| history
src/nvc.c		diff \| blob \| history
src/rt/shell.c		diff \| blob \| history
test/test_elab.c		diff \| blob \| history

VHDL compiler and simulator