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Missing Verilog "or" and "=" operators. Issue #1044
authorNick Gasson <nick@nickg.me.uk>
Sun, 3 Nov 2024 11:25:16 +0000 (11:25 +0000)
committerNick Gasson <nick@nickg.me.uk>
Sun, 3 Nov 2024 12:34:56 +0000 (12:34 +0000)
commit167ad9b6c3dfe0a6d26c1664af286afe0f76ed1b
treea0334c6080eb4c6aba38d8a543a8ba0198bc9ce3tree
parentef8cfd00495375afa3f205ac02a636fa6315e5aecommit | diff
Missing Verilog "or" and "=" operators. Issue #1044
lib/nvc/verilog-body.vhd diff | blob | history
lib/nvc/verilog.vhd diff | blob | history
test/regress/issue1044.v [new file with mode: 0644] blob
test/regress/issue1044.vhd [new file with mode: 0644] blob
test/regress/testlist.txt diff | blob | history
VHDL compiler and simulator