]> Nick Gasson's Git Repositories - nvc.git/commit
New approach to translating Verilog modules
authorNick Gasson <nick@nickg.me.uk>
Sun, 28 Jan 2024 11:27:17 +0000 (11:27 +0000)
committerNick Gasson <nick@nickg.me.uk>
Sun, 28 Jan 2024 11:27:17 +0000 (11:27 +0000)
commit174cc937948e762c170d95536ccb9cb6eba2278a
treeebaaaa3bd66dd504c468430ae77d53535f316495
parent4a5a196e118a8fdbb311957d1442fc6c9c4c4c67
New approach to translating Verilog modules
21 files changed:
lib/nvc/verilog-body.vhd
src/common.c
src/common.h
src/dump.c
src/elab.c
src/jit/jit-irgen.c
src/lower.c
src/lower.h
src/rt/model.c
src/vcode.c
src/vcode.h
src/vlog/Makemodule.am
src/vlog/vlog-dump.c
src/vlog/vlog-lower.c
src/vlog/vlog-node.c
src/vlog/vlog-node.h
src/vlog/vlog-phase.h
src/vlog/vlog-trans.c [new file with mode: 0644]
test/dump/vlog1.v
test/regress/vlog1.vhd
test/test_dump.c