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(parent: 4a5a196) | patch

author	Nick Gasson <nick@nickg.me.uk>
	Sun, 28 Jan 2024 11:27:17 +0000 (11:27 +0000)
committer	Nick Gasson <nick@nickg.me.uk>
	Sun, 28 Jan 2024 11:27:17 +0000 (11:27 +0000)
commit	174cc937948e762c170d95536ccb9cb6eba2278a
tree	ebaaaa3bd66dd504c468430ae77d53535f316495	tree \| snapshot
parent	4a5a196e118a8fdbb311957d1442fc6c9c4c4c67	commit \| diff

New approach to translating Verilog modules

21 files changed:

lib/nvc/verilog-body.vhd		diff \| blob \| history
src/common.c		diff \| blob \| history
src/common.h		diff \| blob \| history
src/dump.c		diff \| blob \| history
src/elab.c		diff \| blob \| history
src/jit/jit-irgen.c		diff \| blob \| history
src/lower.c		diff \| blob \| history
src/lower.h		diff \| blob \| history
src/rt/model.c		diff \| blob \| history
src/vcode.c		diff \| blob \| history
src/vcode.h		diff \| blob \| history
src/vlog/Makemodule.am		diff \| blob \| history
src/vlog/vlog-dump.c		diff \| blob \| history
src/vlog/vlog-lower.c		diff \| blob \| history
src/vlog/vlog-node.c		diff \| blob \| history
src/vlog/vlog-node.h		diff \| blob \| history
src/vlog/vlog-phase.h		diff \| blob \| history
src/vlog/vlog-trans.c	[new file with mode: 0644]	blob
test/dump/vlog1.v		diff \| blob \| history
test/regress/vlog1.vhd		diff \| blob \| history
test/test_dump.c		diff \| blob \| history

VHDL compiler and simulator