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(parent: 7fb9470) | patch

author	Nick Gasson <nick@nickg.me.uk>
	Tue, 27 Feb 2024 21:43:52 +0000 (21:43 +0000)
committer	Nick Gasson <nick@nickg.me.uk>
	Wed, 28 Feb 2024 19:25:52 +0000 (19:25 +0000)
commit	2a43d1637f87e50257df19e83e2150caa8c64a51
tree	bad037798882e9740ff12dac0eeaaa93f71044ac	tree \| snapshot
parent	7fb9470d5dbe2b732a187883c8d3fdaedf9a2ab0	commit \| diff

Implement Verilog case equality

lib/nvc/verilog-body.vhd		diff \| blob \| history
lib/nvc/verilog.vhd		diff \| blob \| history
src/lexer.l		diff \| blob \| history
src/scan.c		diff \| blob \| history
src/scan.h		diff \| blob \| history
src/vlog/vlog-lower.c		diff \| blob \| history
src/vlog/vlog-node.h		diff \| blob \| history
src/vlog/vlog-parse.y		diff \| blob \| history
test/regress/testlist.txt		diff \| blob \| history
test/regress/vlog8.v	[new file with mode: 0644]	blob
test/run_regr.c		diff \| blob \| history

VHDL compiler and simulator