git.nickg.me.uk Git - nvc.git/commit

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(parent: bf7e23c) | patch

author	Nick Gasson <nick@nickg.me.uk>
	Tue, 10 Oct 2023 19:23:19 +0000 (20:23 +0100)
committer	Nick Gasson <nick@nickg.me.uk>
	Tue, 10 Oct 2023 19:38:40 +0000 (20:38 +0100)
commit	2b3e08b3988ae635866f09bef9dcb605c9e7eb4c
tree	1d542ec8489cec43a2d5f4194bc22f3fe55e740a	tree \| snapshot
parent	bf7e23c1187cc01fe9673d0af2ac804a2b6fb04b	commit \| diff

Verilog continuous assignment and binary "&"

lib/nvc/verilog-body.vhd		diff \| blob \| history
lib/nvc/verilog.vhd		diff \| blob \| history
src/rt/model.c		diff \| blob \| history
src/vlog/vlog-lower.c		diff \| blob \| history
src/vlog/vlog-node.c		diff \| blob \| history
src/vlog/vlog-parse.y		diff \| blob \| history
test/regress/gold/vlog5.txt	[new file with mode: 0644]	blob
test/regress/testlist.txt		diff \| blob \| history
test/regress/vlog5.v	[new file with mode: 0644]	blob

VHDL compiler and simulator