]> Nick Gasson's Git Repositories - nvc.git/commit
Implement `ifdef, `ifndef, etc. in Verilog preprocessor
authorNick Gasson <nick@nickg.me.uk>
Fri, 14 Jun 2024 18:45:31 +0000 (19:45 +0100)
committerNick Gasson <nick@nickg.me.uk>
Fri, 14 Jun 2024 18:45:31 +0000 (19:45 +0100)
commit2c6627618955c3c7cefda7a8224a22fed1cb0f51
treee6996316561a44f2b7b733eb1bd6276b3edaf080
parenta6f48cf3b184fe99f7b44aa78d4afc3b38975902
Implement `ifdef, `ifndef, etc. in Verilog preprocessor
src/vlog/vlog-pp.l
test/test_vlog.c
test/vlog/pp1.v
test/vlog/pp2.v [new file with mode: 0644]