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(parent: cd5f13d) | patch

author	Nick Gasson <nick@nickg.me.uk>
	Mon, 30 Dec 2024 20:17:06 +0000 (20:17 +0000)
committer	Nick Gasson <nick@nickg.me.uk>
	Tue, 31 Dec 2024 09:50:22 +0000 (09:50 +0000)
commit	2ce462d68368700d338b4e6fcbc7da3c432dd150
tree	c389dde1cdd3727caff05c05254de7d24bde9178	tree
parent	cd5f13ddd1c622f088f84142819641433f6a1938	commit \| diff

Define Verilog preprocessor macros on command line

Based on code from @Blebowski in #1110

14 files changed:

nvc.1		diff \| blob \| history
src/hash.c		diff \| blob \| history
src/hash.h		diff \| blob \| history
src/nvc.c		diff \| blob \| history
src/option.c		diff \| blob \| history
src/option.h		diff \| blob \| history
src/scan.c		diff \| blob \| history
src/scan.h		diff \| blob \| history
src/util.c		diff \| blob \| history
src/util.h		diff \| blob \| history
src/vlog/vlog-pp.l		diff \| blob \| history
src/vpi/vpi-systf.c		diff \| blob \| history
test/regress/cmdline13.sh	[new file with mode: 0644]	blob
test/regress/testlist.txt		diff \| blob \| history

VHDL compiler and simulator