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(parent: 829f19c) | patch

author	Nick Gasson <nick@nickg.me.uk>
	Sat, 20 Apr 2024 16:34:54 +0000 (17:34 +0100)
committer	Nick Gasson <nick@nickg.me.uk>
	Sat, 20 Apr 2024 16:34:54 +0000 (17:34 +0100)
commit	309579f0910f31f7e3cab55f9a2651529cd29de3
tree	689019fc7f805ea6e37c1094fa2e1fe9e4e660f3	tree
parent	829f19c567596d5c178641d91ec405fa55b107bf	commit \| diff

Lowering for delays in Verilog procedural assignments

12 files changed:

lib/nvc/verilog-body.vhd		diff \| blob \| history
lib/nvc/verilog.vhd		diff \| blob \| history
src/rt/verilog.c		diff \| blob \| history
src/vlog/vlog-lower.c		diff \| blob \| history
src/vlog/vlog-node.c		diff \| blob \| history
src/vlog/vlog-number.c		diff \| blob \| history
test/regress/gold/ivtest2.txt	[new file with mode: 0644]	blob
test/regress/ivtest1.v	[new file with mode: 0644]	blob
test/regress/ivtest2.v	[new file with mode: 0644]	blob
test/regress/testlist.txt		diff \| blob \| history
test/regress/vlog9.v	[deleted file]	blob \| history
test/test_vlog.c		diff \| blob \| history

VHDL compiler and simulator