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(parent: 67753a1) | patch
Generate constraints for port with unconstrained record type. Issue #544
authorNick Gasson <nick@nickg.me.uk>
Tue, 11 Oct 2022 21:08:27 +0000 (22:08 +0100)
committerNick Gasson <nick@nickg.me.uk>
Tue, 11 Oct 2022 21:19:24 +0000 (22:19 +0100)
commit31cece974ae5bcffd1c5222b20cefd125e4e8901
tree3ed10031c3d3cfbea69e79e02e5f22d9b5e0f60etree | snapshot
parent67753a17c6d1e5961a83c0320ab689edc4a0dea1commit | diff
Generate constraints for port with unconstrained record type. Issue #544
src/elab.c diff | blob | history
src/lower.c diff | blob | history
test/regress/issue544.vhd [new file with mode: 0644] blob
test/regress/testlist.txt diff | blob | history
VHDL compiler and simulator