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(parent: ea5d1d6) | patch

author	Nick Gasson <nick@nickg.me.uk>
	Sun, 22 Oct 2023 14:51:14 +0000 (15:51 +0100)
committer	Nick Gasson <nick@nickg.me.uk>
	Sun, 22 Oct 2023 16:08:44 +0000 (17:08 +0100)
commit	35981ac140233cb8d66e50eeea070ad957359916
tree	2e7389f1903cd4a3a5e5850bdca4503e44625a18	tree \| snapshot
parent	ea5d1d6bb5215332e8e4bce886448f23fd312a56	commit \| diff

Integrate Verilog preprocessor with parser

src/common.c		diff \| blob \| history
src/nvc.c		diff \| blob \| history
src/object.c		diff \| blob \| history
src/scan.c		diff \| blob \| history
src/scan.h		diff \| blob \| history
src/vlog/vlog-phase.h		diff \| blob \| history
src/vlog/vlog-pp.l		diff \| blob \| history
test/regress/vlog2.v		diff \| blob \| history
test/test_vlog.c		diff \| blob \| history

VHDL compiler and simulator