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(parent: 19f67b7) | patch
Constrain ports during code generation. Fixes #809
authorNick Gasson <nick@nickg.me.uk>
Fri, 1 Dec 2023 19:53:09 +0000 (19:53 +0000)
committerNick Gasson <nick@nickg.me.uk>
Fri, 1 Dec 2023 20:15:58 +0000 (20:15 +0000)
commit3ad97cfe36e873b24f853c98b3bf4e3c9104bc00
tree2da6e52f6d3c65bfc6139b5b9aa3d9d2608d9d70tree | snapshot
parent19f67b74133d6eb1dde27799dae59d47578554b2commit | diff
Constrain ports during code generation. Fixes #809
13 files changed:
.gitignore diff | blob | history
src/elab.c diff | blob | history
src/lower.c diff | blob | history
src/rt/wave.c diff | blob | history
src/sem.c diff | blob | history
src/simp.c diff | blob | history
src/tree.h diff | blob | history
test/regress/elab32.vhd diff | blob | history
test/regress/gold/issue586.dump diff | blob | history
test/regress/issue809.vhd [new file with mode: 0644] blob
test/regress/range3.vhd [new file with mode: 0644] blob
test/regress/testlist.txt diff | blob | history
test/test_lower.c diff | blob | history
VHDL compiler and simulator