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Rework determination of most recently analysed architecture
authorNick Gasson <nick@nickg.me.uk>
Sat, 17 Jun 2023 15:19:07 +0000 (16:19 +0100)
committerNick Gasson <nick@nickg.me.uk>
Sat, 17 Jun 2023 16:20:08 +0000 (17:20 +0100)
commit4bb791f081661c0b1c9255515bfae1fc6ec3bf78
treebde4548d50b636b6f0f4579d0b74174319cbdefftree | snapshot
parentbc5007a5ec10980698be892b17b4ba14906b6d0bcommit | diff
Rework determination of most recently analysed architecture

Avoid using timestamps as well as loading every architecture and instead
establish a total order over all architectures in a library with a new
_sequence file.

Issue #715
Issue #710
src/elab.c diff | blob | history
src/fbuf.c diff | blob | history
src/fbuf.h diff | blob | history
src/lib.c diff | blob | history
src/lib.h diff | blob | history
src/util.h diff | blob | history
test/regress/issue715.sh [new file with mode: 0644] blob
test/regress/testlist.txt diff | blob | history
VHDL compiler and simulator