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(parent: b50e3b5) | patch

author	Nick Gasson <nick@nickg.me.uk>
	Fri, 22 Sep 2023 19:43:01 +0000 (20:43 +0100)
committer	Nick Gasson <nick@nickg.me.uk>
	Fri, 22 Sep 2023 19:43:01 +0000 (20:43 +0100)
commit	4e1df74a60d0e39b3ebf42c8319062034dab7b7f
tree	136170a24c2a08f5879e650e7729f3a6625b492c	tree \| snapshot
parent	b50e3b52fb0be6f6fd4894896143c9bb3251f85e	commit \| diff

Lowering for Verilog variables with packed dimensions

lib/nvc/verilog-body.vhd		diff \| blob \| history
lib/nvc/verilog.vhd		diff \| blob \| history
src/rt/verilog.c		diff \| blob \| history
src/vcode.c		diff \| blob \| history
src/vlog/vlog-lower.c		diff \| blob \| history
src/vlog/vlog-parse.y		diff \| blob \| history
test/regress/gold/vlog2.txt		diff \| blob \| history
test/regress/gold/vlog4.txt	[new file with mode: 0644]	blob
test/regress/testlist.txt		diff \| blob \| history
test/regress/vlog4.v	[new file with mode: 0644]	blob

VHDL compiler and simulator