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Exclude Verilog preprocessor from coverage collection
authorNick Gasson <nick@nickg.me.uk>
Sun, 22 Oct 2023 10:50:19 +0000 (11:50 +0100)
committerNick Gasson <nick@nickg.me.uk>
Sun, 22 Oct 2023 10:50:19 +0000 (11:50 +0100)
commit4fe302b914c0e9d998d2ff0277045c8b806444b1
treeddd18b5f3ea2476edeba86a3ed3d227379af9466tree | snapshot
parentef3e49239c581b7803cb73597ca3389e0bbbe65acommit | diff
Exclude Verilog preprocessor from coverage collection
test/Makemodule.am diff | blob | history
VHDL compiler and simulator