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(parent: 51b5f02) | patch

author	Nick Gasson <nick@nickg.me.uk>
	Sun, 12 Nov 2023 21:00:08 +0000 (21:00 +0000)
committer	Nick Gasson <nick@nickg.me.uk>
	Sun, 12 Nov 2023 21:00:08 +0000 (21:00 +0000)
commit	581e958f627e6c32c9a69b3e4089c7781530aa8e
tree	e396b3711e98af072859cada38d0ba13ab4a2b8c	tree \| snapshot
parent	51b5f02537461a110f82ea5ffd7dbb5875862e60	commit \| diff

Single elaboration function for Verilog and VHDL

src/elab.c		diff \| blob \| history
src/nvc.c		diff \| blob \| history
src/phase.h		diff \| blob \| history
src/rt/shell.c		diff \| blob \| history
test/test_elab.c		diff \| blob \| history
test/test_lower.c		diff \| blob \| history
test/test_util.c		diff \| blob \| history

VHDL compiler and simulator