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(parent: 5d630f7) | patch
Rejig the layout of signals again
authorNick Gasson <nick@nickg.me.uk>
Sun, 11 Jul 2021 07:02:06 +0000 (15:02 +0800)
committerNick Gasson <nick@nickg.me.uk>
Sun, 8 Aug 2021 08:16:14 +0000 (16:16 +0800)
commit626644c4731cb153c9d2ba64a7aff667dbe19e34
tree4014bd46062f820e6d4f83a9b7f49dcd69f7e8bftree | snapshot
parent5d630f7ebe98fc4fe96706ca4b79e3f80c9e91bfcommit | diff
Rejig the layout of signals again
src/cgen.c diff | blob | history
src/eval.c diff | blob | history
src/lower.c diff | blob | history
src/rt/rtkern.c diff | blob | history
src/vcode.c diff | blob | history
src/vcode.h diff | blob | history
test/group/signal3.vhd [new file with mode: 0644] blob
test/test_elab.c diff | blob | history
VHDL compiler and simulator