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(parent: e15226d) | patch
Add a test for pulse rejection limit
authorNick Gasson <nick@nickg.me.uk>
Wed, 21 Sep 2022 20:22:49 +0000 (21:22 +0100)
committerNick Gasson <nick@nickg.me.uk>
Wed, 21 Sep 2022 20:22:49 +0000 (21:22 +0100)
commit7099a71495be96afd5b5417ae736919c0b07b049
treef7066da4bc418366892d0204a2b54745e247457btree | snapshot
parente15226d5e6755e30d40cc3c2245e1948828d59fccommit | diff
Add a test for pulse rejection limit
src/rt/model.c diff | blob | history
test/regress/delay3.vhd [new file with mode: 0644] blob
test/regress/gold/delay3.txt [new file with mode: 0644] blob
test/regress/testlist.txt diff | blob | history
VHDL compiler and simulator