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(parent: 8eaae16) | patch

author	Nick Gasson <nick@nickg.me.uk>
	Fri, 22 Sep 2023 10:37:22 +0000 (11:37 +0100)
committer	Nick Gasson <nick@nickg.me.uk>
	Fri, 22 Sep 2023 10:37:22 +0000 (11:37 +0100)
commit	87015b6fe66f50a7047bb807ebe0ee7da3244074
tree	5db9b993920eba4e25a213a0bd64f19b036928b2	tree \| snapshot
parent	8eaae1660d47ca50da802d319ac542354ef80195	commit \| diff

Lowering for Verilog if statements

lib/nvc/verilog-body.vhd		diff \| blob \| history
src/lexer.l		diff \| blob \| history
src/vlog/vlog-dump.c		diff \| blob \| history
src/vlog/vlog-lower.c		diff \| blob \| history
src/vlog/vlog-node.c		diff \| blob \| history
src/vlog/vlog-node.h		diff \| blob \| history
src/vlog/vlog-parse.y		diff \| blob \| history
src/vlog/vlog-sem.c		diff \| blob \| history
test/regress/vlog3.v		diff \| blob \| history
test/test_vlog.c		diff \| blob \| history
test/vlog/parse1.v		diff \| blob \| history

VHDL compiler and simulator