]> Nick Gasson's Git Repositories - nvc.git/commit
Code generation for Verilog primitive gates
authorNick Gasson <nick@nickg.me.uk>
Sat, 17 Aug 2024 20:49:23 +0000 (21:49 +0100)
committerNick Gasson <nick@nickg.me.uk>
Sat, 17 Aug 2024 20:49:23 +0000 (21:49 +0100)
commit929d4af9ba2753e3eaa38d534354bfcfc69e3fa2
treeb7c4893c2d1dd74ee2e74d5f09ff19242af9acbd
parent4ef2226b7680456f9f789e7256c2f83780bf717b
Code generation for Verilog primitive gates
lib/nvc/verilog-body.vhd
lib/nvc/verilog.vhd
src/vlog/vlog-lower.c
test/regress/testlist.txt
test/regress/vlog10.v [new file with mode: 0644]
test/regress/vlog11.v [new file with mode: 0644]