Nick Gasson's Git Repositories - nvc.git/commit

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(parent: 589e28a) | patch

author	Nick Gasson <nick@nickg.me.uk>
	Sun, 26 Nov 2023 13:59:59 +0000 (13:59 +0000)
committer	Nick Gasson <nick@nickg.me.uk>
	Sun, 26 Nov 2023 13:59:59 +0000 (13:59 +0000)
commit	9aac45c43ed62fb5f754b1820e076a640829d5af
tree	38546b08175bc26486f37066ec0110a4d94a35e8	tree
parent	589e28af47d44ee89c9852866b2a6f3bcec6f604	commit \| diff

Add support for Verilog unary ~ and ! operators

16 files changed:

lib/nvc/verilog-body.vhd		diff \| blob \| history
lib/nvc/verilog.vhd		diff \| blob \| history
src/common.c		diff \| blob \| history
src/common.h		diff \| blob \| history
src/elab.c		diff \| blob \| history
src/lexer.l		diff \| blob \| history
src/scan.h		diff \| blob \| history
src/vlog/vlog-lower.c		diff \| blob \| history
src/vlog/vlog-node.c		diff \| blob \| history
src/vlog/vlog-node.h		diff \| blob \| history
src/vlog/vlog-parse.y		diff \| blob \| history
src/vlog/vlog-sem.c		diff \| blob \| history
test/regress/gold/vlog6.txt	[new file with mode: 0644]	blob
test/regress/testlist.txt		diff \| blob \| history
test/regress/vlog6.v	[new file with mode: 0644]	blob
test/vlog/parse1.v		diff \| blob \| history

VHDL compiler and simulator