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(parent: d83d552) | patch

author	Nick Gasson <nick@nickg.me.uk>
	Fri, 14 Jul 2023 10:59:02 +0000 (11:59 +0100)
committer	Nick Gasson <nick@nickg.me.uk>
	Fri, 14 Jul 2023 11:01:11 +0000 (12:01 +0100)
commit	a1d2f27598230b5ebf3b7655c2a83f3c40706b3d
tree	4ce926eb76272109323e440de1c282b4db6a3145	tree \| snapshot
parent	d83d552d4c6fde6c865f1aec050bfde9d1e0fc32	commit \| diff

Include Verilog test files in distribution

test/Makemodule.am		diff \| blob \| history
test/dist.mk		diff \| blob \| history

VHDL compiler and simulator