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(parent: 1745c08) | patch

author	Nick Gasson <nick@nickg.me.uk>
	Tue, 23 Apr 2024 19:40:58 +0000 (20:40 +0100)
committer	Nick Gasson <nick@nickg.me.uk>
	Tue, 23 Apr 2024 19:40:58 +0000 (20:40 +0100)
commit	ac419477e7032c353a2b56ae711c375e5d5563b9
tree	ba79ec93f703b896da52877363d63b360ebdcdab	tree \| snapshot
parent	1745c08118eab920908799ee09bc71edd46640e7	commit \| diff

Verilog unary negation

lib/nvc/verilog-body.vhd		diff \| blob \| history
lib/nvc/verilog.vhd		diff \| blob \| history
src/vlog/vlog-lower.c		diff \| blob \| history
src/vlog/vlog-node.h		diff \| blob \| history
src/vlog/vlog-number.c		diff \| blob \| history
src/vlog/vlog-parse.y		diff \| blob \| history
test/regress/ivtest3.v	[new file with mode: 0644]	blob
test/regress/testlist.txt		diff \| blob \| history
test/test_vlog.c		diff \| blob \| history

VHDL compiler and simulator