]> git.nickg.me.uk Git - nvc.git/commit
Add basic support for VHDL-2017 conditional analysis blocks
authorNick Gasson <nick@nickg.me.uk>
Sat, 30 Sep 2017 11:48:41 +0000 (12:48 +0100)
committerNick Gasson <nick@nickg.me.uk>
Sat, 30 Sep 2017 11:48:41 +0000 (12:48 +0100)
commitbccbd4e8e32d13a8114dff165159edccd832eeef
tree48254c90e70adec5b6d2c0fc7ddfb27707c42bde
parent2ac40252ef030bcf111ac31319d693ea0348656b
Add basic support for VHDL-2017 conditional analysis blocks
src/lexer.l
src/parse.c
src/token.h
test/parse/cond1.vhd [new file with mode: 0644]
test/test_parse.c