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(parent: 10c478f) | patch

author	Nick Gasson <nick@nickg.me.uk>
	Sat, 21 Oct 2023 09:34:45 +0000 (10:34 +0100)
committer	Nick Gasson <nick@nickg.me.uk>
	Sat, 21 Oct 2023 09:34:45 +0000 (10:34 +0100)
commit	ca4480aa95a30faf30be626569f50de6ba0fb8ed
tree	a1797282715ece96832c6e6f90ab23f357138622	tree \| snapshot
parent	10c478f3f992ef1b2268f34f1b055acafc766b3d	commit \| diff

Add Verilog preprocessor step

Makefile.am		diff \| blob \| history
src/nvc.c		diff \| blob \| history
src/vlog/Makemodule.am		diff \| blob \| history
src/vlog/vlog-phase.h		diff \| blob \| history
src/vlog/vlog-pp.l	[new file with mode: 0644]	blob
test/test_vlog.c		diff \| blob \| history
test/vlog/pp1.v	[new file with mode: 0644]	blob

VHDL compiler and simulator