]> git.nickg.me.uk Git - nvc.git/commit
Verilog bit selects
authorNick Gasson <nick@nickg.me.uk>
Thu, 29 Feb 2024 19:24:23 +0000 (19:24 +0000)
committerNick Gasson <nick@nickg.me.uk>
Thu, 29 Feb 2024 19:24:23 +0000 (19:24 +0000)
commitcdcac65bd38bde61c512c394af7fe4656f2bbb55
tree84296490a0de2ff27bebe6de37995ae7e11f2aeb
parent79fdfa9e76d846f7d5b37a04fb708f3f1235cd8a
Verilog bit selects
24 files changed:
lib/nvc/verilog-body.vhd
lib/nvc/verilog.vhd
src/common.c
src/common.h
src/elab.c
src/lexer.l
src/scan.c
src/scan.h
src/vlog/vlog-defs.h
src/vlog/vlog-dump.c
src/vlog/vlog-lower.c
src/vlog/vlog-node.c
src/vlog/vlog-node.h
src/vlog/vlog-number.c
src/vlog/vlog-number.h
src/vlog/vlog-parse.y
src/vlog/vlog-sem.c
src/vlog/vlog-trans.c
test/dump/vlog1.v
test/regress/testlist.txt
test/regress/vlog9.v [new file with mode: 0644]
test/test_dump.c
test/test_vlog.c
test/vlog/ports.v