git.nickg.me.uk Git - nvc.git/commit

]> git.nickg.me.uk Git - nvc.git/commit

projects / nvc.git / commit

summary | shortlog | log | commit | commitdiff | tree
(parent: 5fab8a7) | patch

author	Nick Gasson <nick@nickg.me.uk>
	Sat, 24 Feb 2024 10:42:23 +0000 (10:42 +0000)
committer	Nick Gasson <nick@nickg.me.uk>
	Sat, 24 Feb 2024 10:42:23 +0000 (10:42 +0000)
commit	cf5bbb7d3f4c6cdf5224dd2e5c84c538df2935e0
tree	33f665484a7214dd34e5e1e2bb713a4952aa3309	tree \| snapshot
parent	5fab8a70431a3bf2d470c16714a49cfe1edae0fd	commit \| diff

Introduce a cache for translated Verilog modules

src/common.c		diff \| blob \| history
src/elab.c		diff \| blob \| history
src/vlog/vlog-dump.c		diff \| blob \| history
src/vlog/vlog-lower.c		diff \| blob \| history
src/vlog/vlog-phase.h		diff \| blob \| history
src/vlog/vlog-trans.c		diff \| blob \| history
test/dump/vlog1.v		diff \| blob \| history
test/test_dump.c		diff \| blob \| history

VHDL compiler and simulator