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(parent: 1f52a4e) | patch
Add stub for Verilog parser
authorNick Gasson <nick@nickg.me.uk>
Sat, 1 Jan 2022 06:21:27 +0000 (14:21 +0800)
committerNick Gasson <nick@nickg.me.uk>
Fri, 10 Mar 2023 15:38:47 +0000 (15:38 +0000)
commitea9c6bf02775d653f5f9526f3d0a35d49284b731
tree12e7e26ea2b4c1b7a67ee5cb66b14fbb9b8af259tree | snapshot
parent1f52a4e2a51fdd462803f6ad94f09081cfb824d0commit | diff
Add stub for Verilog parser
28 files changed:
.github/workflows/build-test.yml diff | blob | history
configure.ac diff | blob | history
src/common.c diff | blob | history
src/common.h diff | blob | history
src/lexer.l diff | blob | history
src/lib.c diff | blob | history
src/lib.h diff | blob | history
src/nvc.c diff | blob | history
src/object.c diff | blob | history
src/parse.c diff | blob | history
src/scan.c diff | blob | history
src/scan.h diff | blob | history
src/vlog/Makemodule.am diff | blob | history
src/vlog/vlog-dump.c diff | blob | history
src/vlog/vlog-node.c diff | blob | history
src/vlog/vlog-parse.y [new file with mode: 0644] blob
src/vlog/vlog-phase.h diff | blob | history
src/vlog/vlog-sem.c [new file with mode: 0644] blob
test/Makemodule.am diff | blob | history
test/regress/vlog1.v [new file with mode: 0644] blob
test/regress/vlog1.vhd [new file with mode: 0644] blob
test/regress/vlog2.v [new file with mode: 0644] blob
test/run_regr.c diff | blob | history
test/test_vlog.c [new file with mode: 0644] blob
test/unit_test.c diff | blob | history
test/vlog/dff.v [new file with mode: 0644] blob
test/vlog/ports.v [new file with mode: 0644] blob
test/vlog/simple_sem.v [new file with mode: 0644] blob
VHDL compiler and simulator