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(parent: cf5bbb7) | patch

author	Nick Gasson <nick@nickg.me.uk>
	Sat, 24 Feb 2024 11:04:25 +0000 (11:04 +0000)
committer	Nick Gasson <nick@nickg.me.uk>
	Sat, 24 Feb 2024 11:18:43 +0000 (11:18 +0000)
commit	0f928f155c779abe481918efc3df04dd1785f0e9
tree	7bfaa1f8ad773445c617b515eda1f72b808e79dc	tree \| snapshot
parent	cf5bbb7d3f4c6cdf5224dd2e5c84c538df2935e0	commit \| diff

Add support for Verilog supply net type. Issue #808

16 files changed:

src/common.c		diff \| blob \| history
src/elab.c		diff \| blob \| history
src/object.c		diff \| blob \| history
src/vlog/Makemodule.am		diff \| blob \| history
src/vlog/vlog-defs.h	[new file with mode: 0644]	blob
src/vlog/vlog-lower.c		diff \| blob \| history
src/vlog/vlog-node.c		diff \| blob \| history
src/vlog/vlog-node.h		diff \| blob \| history
src/vlog/vlog-number.c		diff \| blob \| history
src/vlog/vlog-parse.y		diff \| blob \| history
src/vlog/vlog-phase.h		diff \| blob \| history
src/vlog/vlog-simp.c	[new file with mode: 0644]	blob
src/vlog/vlog-trans.c		diff \| blob \| history
test/regress/gold/issue808.txt	[new file with mode: 0644]	blob
test/regress/issue808.v	[new file with mode: 0644]	blob
test/regress/testlist.txt		diff \| blob \| history

VHDL compiler and simulator