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(parent: 75fb8a7) | patch

author	Nick Gasson <nick@nickg.me.uk>
	Sun, 22 Oct 2023 16:00:19 +0000 (17:00 +0100)
committer	Nick Gasson <nick@nickg.me.uk>
	Sun, 22 Oct 2023 16:08:46 +0000 (17:08 +0100)
commit	6cda7f4e365e29c292406f2bc6bcf3c2357b462e
tree	cc66618f32ac5d773edc11e32b7b9669e6c8df4b	tree \| snapshot
parent	75fb8a7bd02ba2a1c35c28807abff25a227dd41e	commit \| diff

Parse Verilog inout ports

src/lexer.l		diff \| blob \| history
src/vlog/vlog-parse.y		diff \| blob \| history
test/vlog/ports.v		diff \| blob \| history

VHDL compiler and simulator