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(parent: 35981ac) | patch

author	Nick Gasson <nick@nickg.me.uk>
	Sun, 22 Oct 2023 15:55:53 +0000 (16:55 +0100)
committer	Nick Gasson <nick@nickg.me.uk>
	Sun, 22 Oct 2023 16:08:46 +0000 (17:08 +0100)
commit	75fb8a7bd02ba2a1c35c28807abff25a227dd41e
tree	c2a46ebf2554c480ed9d2ebdfbdd6833cec25f58	tree \| snapshot
parent	35981ac140233cb8d66e50eeea070ad957359916	commit \| diff

Parse Verilog timescale directive

src/lexer.l		diff \| blob \| history
src/scan.c		diff \| blob \| history
src/scan.h		diff \| blob \| history
src/vlog/vlog-parse.y		diff \| blob \| history
src/vlog/vlog-pp.l		diff \| blob \| history
test/test_vlog.c		diff \| blob \| history
test/vlog/timescale1.v	[new file with mode: 0644]	blob

VHDL compiler and simulator