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(parent: e093a11) | patch

author	Nick Gasson <nick@nickg.me.uk>
	Sun, 25 Feb 2024 19:12:36 +0000 (19:12 +0000)
committer	Nick Gasson <nick@nickg.me.uk>
	Sun, 25 Feb 2024 19:12:36 +0000 (19:12 +0000)
commit	c7b8eea3657eea5c6bb107fc37ea044e0bbb06a1
tree	1a360a62bb99d1c830ecfcc1ad5e7c3aff440533	tree \| snapshot
parent	e093a1117e38793e0c32b0c29fd6e8e70fb0c0ed	commit \| diff

Add some basic support for Verilog module instantiation

14 files changed:

src/dump.c		diff \| blob \| history
src/elab.c		diff \| blob \| history
src/vlog/vlog-dump.c		diff \| blob \| history
src/vlog/vlog-lower.c		diff \| blob \| history
src/vlog/vlog-node.c		diff \| blob \| history
src/vlog/vlog-node.h		diff \| blob \| history
src/vlog/vlog-parse.y		diff \| blob \| history
src/vlog/vlog-sem.c		diff \| blob \| history
test/dump/vlog1.v		diff \| blob \| history
test/elab/vlog1.v	[new file with mode: 0644]	blob
test/regress/gold/issue808.txt		diff \| blob \| history
test/regress/issue808.v		diff \| blob \| history
test/test_dump.c		diff \| blob \| history
test/test_elab.c		diff \| blob \| history

VHDL compiler and simulator