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(parent: 0f928f1) | patch

author	Nick Gasson <nick@nickg.me.uk>
	Sun, 25 Feb 2024 16:18:56 +0000 (16:18 +0000)
committer	Nick Gasson <nick@nickg.me.uk>
	Sun, 25 Feb 2024 16:18:56 +0000 (16:18 +0000)
commit	e093a1117e38793e0c32b0c29fd6e8e70fb0c0ed
tree	c269430d533552e8035c5d644a7e779a9aca9652	tree \| snapshot
parent	0f928f155c779abe481918efc3df04dd1785f0e9	commit \| diff

Refactor parsing of Verilog port declarations

14 files changed:

src/vlog/Makemodule.am		diff \| blob \| history
src/vlog/vlog-dump.c		diff \| blob \| history
src/vlog/vlog-lower.c		diff \| blob \| history
src/vlog/vlog-node.c		diff \| blob \| history
src/vlog/vlog-node.h		diff \| blob \| history
src/vlog/vlog-parse.y		diff \| blob \| history
src/vlog/vlog-sem.c		diff \| blob \| history
src/vlog/vlog-simp.c		diff \| blob \| history
src/vlog/vlog-trans.c		diff \| blob \| history
src/vlog/vlog-util.c	[new file with mode: 0644]	blob
src/vlog/vlog-util.h	[new file with mode: 0644]	blob
test/test_dump.c		diff \| blob \| history
test/test_vlog.c		diff \| blob \| history
test/vlog/ports.v		diff \| blob \| history

VHDL compiler and simulator